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US 2012/0068753 A1Published application
Analog delay lines and adaptive biasing
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
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Abstract
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.
Claims32
An analog delay line system comprising:
- an analog delay line comprising a plurality of analog delay elements, individual ones of the plurality of analog delay elements configured to receive a bias signal and a respective periodic input signal and delay the respective periodic input signal to provide a periodic output signal generate a respective delayed periodic output signal, wherein the respective periodic input signal of each one of the delay elements coupled to an output of another one of the delay elements comprises a respective one of the delayed periodic output signals, and wherein an amount of delay is based, at least in part, on the bias current signal;
- frequency measurement circuitry coupled to at least a portion of the analog delay line and configured to measure a frequency of at least one of said respective periodic input signals, the frequency measurement circuitry configured to provide a control signal based, at least in part, on the frequency of the at least one of said respective periodic input signals;
- and
- bias control circuitry configured to receive the control signal and further configured to generate the bias signal based, at least in part, on the frequency of the at least one of said respective periodic input signals.
1 more element
A system comprising:
- an analog delay line configured to receive a bias and an input signal, and delay the input signal to provide a delayed output signal based, at least in part, on the bias;
- frequency measurement circuitry configured to measure a frequency of operation of the analog delay line and to provide an indication of the frequency of operation;
- and
- bias control circuitry configured to receive the indication of the frequency of operation and to generate the bias, wherein the bias is based, at least in part, on the frequency of operation.
1 more element
An adaptive bias circuit for use with an analog delay line, the adaptive bias circuit comprising:
- an operational amplifier configured to receive a control signal and a feedback signal and further configured to generate a first bias signal based, at least in part on a comparison of the control signal and the feedback signal;
- a first transistor configured to receive the control signal at a gate of the first transistor;
- and
- a second transistor having a gate coupled to a source/drain terminal of the second transistor, and wherein the source/drain of the second transistor is coupled to source/drain of the first transistor, and wherein the second transistor is configured to generate the feedback signal at the gate of the second transistor, wherein the gate of the second transistor is coupled to the operational amplifier to provide the feedback signal to the operational amplifier.
1 more element
A method of biasing an analog delay line, the method comprising:
- measuring a frequency of operation of the analog delay line;
- generating a bias based, at least in part, on the frequency of operation of the analog delay line;
- and
- providing the bias to the analog delay line, wherein the analog delay line is configured to delay an input signal by an amount based, at least in part, on the bias.
1 more element
Dependencies are inferred from the claim text.