Method and apparatus for improving accuracy of signals delay

A digital locked loop (DLL), comprising a clock detection apparatus, adapted to detect a clock period to be detected, wherein the clock detection apparatus comprises:

• a delay module comprising:
• a first delay unit;
• a second delay unit;
• an inverter;
• wherein, each of the first delay unit and the second delay unit comprises a logic gate for gating and a logic gate for delaying, the two logic gates have the function of invert a phase, an output port of the logic gate for gating electrically connected to an input port of the logic gate for delaying;
• an input port of the logic gate for gating of the first delay unit is electrically connected to an output port of the inverter, and an output port of the logic gate for delaying of the first delay unit is electrically connect to an input port of the logic gate for delaying of the second delay unit;
• an input port of the inverter is electrically connected to an input port of the logic gate for gating of the second delay unit;
• and
• the input port of the inverter is adapted to input a clock signal to be delayed, and the logic gate for delaying of the second delay unit is adapted to output a delayed clock signal;
• an adjusting module comprising:
• at least two adjusting units, wherein, each of the adjusting units comprises a NOT gate and a selecting inverter an output port of the NOT gate of each of the adjusting units is electrically connected to an input port of each selecting inverter, the NOT gates of the adjusting units are mutually cascaded each other and the selecting inverters of the adjusting units mutually cascaded each other;
• and
• an input port of a NOT gate of one adjusting unit is adapted to input a clock signal to be detected, and the selecting inverter of the one adjusting unit is adapted to output the delayed clock signal to the delay module as a clock signal to be delayed of the delay module.