US 2012/0068744 A1 · Phase Locked Loop Circuits

Abstract

A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selector, a dividing unit, a converter, a low pass filer (LPF), and a modulator. The selector selects one of the internal clock signals to serve as a selection clock signal according to an enable signal. The first dividing unit performs dividing operations to the selection clock signal to generate the output clock signal and a feedback clock signal. The converter detects phase difference between the feedback clock signal and a reference clock signal to generate a detection signal. The LPF performs a filtering operation to the detection signal to generate a filtering signal. The modulator modulates the filtering signal to generate the enable signal.

Claims20

Dependent claims

A phase locked loop (PLL) circuit for receiving an input clock signal and generating an output clock signal according to a plurality of internal clock signals with phase shifting which are generated according to the input clock signal, the PLL circuit comprising:

a selector for receiving the internal clock signals and outputting a selection clock signal, wherein the selector selects one of the internal clock signals to serve as the selection clock signal according to an enable signal;
a first dividing unit for receiving the selection clock signal and performing dividing operations to the selection clock signal to generate the output clock signal and a first feedback clock signal;
a converter for receiving the feedback clock signal and a reference clock signal and detecting phase difference between the first feedback clock signal and the reference clock signal to generate a detection signal;
a first low pass filer for receiving the detection signal and performing a filtering operation to the detection signal to generate a filtering signal;
and
a modulator for receiving and modulating the filtering signal to generate the enable signal.

3 more elements

A dual-loop phase locked loop (PLL) circuit for receiving an input clock signal and generating an output clock signal, comprising:

a first PLL loop for receiving the input clock signal and generating a plurality of internal clock signals with phase shifting according to the input clock signal;
and
a second PLL loop for receiving the internal clock signals and generating the output clock signal according to the internal clock signals, wherein the second PLL loop comprises:
a selector for receiving the internal clock signals and outputting a selection clock signal, wherein the selector selects one of the internal clock signals to serve as the selection clock signal according to an enable signal;
a first dividing unit for receiving the selection clock signal and performing dividing operations to the selection clock signal to generate the output clock signal and a first feedback clock signal;
a converter for receiving the feedback clock signal and a reference clock signal and detecting phase difference between the first feedback clock signal and the reference clock signal to generate a detection signal;
a first low pass filer for receiving the detection signal and performing a filtering operation to the detection signal to generate a filtering signal;
and
a modulator for receiving and modulating the filtering signal to generate the enable signal.

6 more elements

Dependencies are inferred from the claim text.

Phase Locked Loop Circuits

Life of this patent

Phase Locked Loop Circuits

Life of this patent

Abstract

Claims20