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US 2012/0068741 A1Published application
Phase locked loop and method for operating the same
AssigneeHynix Semiconductor Inc.
InventorKwan-Dong KIM
Life of this patent
Estimating the term…
Abstract
A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.
Claims6
1-18. (canceled)
A phase locked loop, comprising:
- a first locking loop configured to generate an internal clock based on a phase of a reference clock and a feedback clock;
- and
- a second locking loop configured to generate the feedback clock which is delayed in response to a control voltage based on a phase of the reference clock and the internal clock.
Dependencies are inferred from the claim text.