Design apparatus, design method and semiconductor integrated circuit

Abstract

A design apparatus according to the present embodiment includes a scheduling section, a group ID assigning section, a transition violation detecting section and a state inserting section. The scheduling section generates a plurality of states that transition based on a clock according to a control data flow graph generated from a behavioral description and common resource schedule information. The group ID assigning section assigns group IDs to the plurality of states under a predetermined condition. The transition violation detecting section detects whether or not there is any transition violation among the plurality of states to which the group IDs are assigned. The state inserting section adds, when a transition violation is detected by the transition violation detecting section, a new state between states from which the transition violation has been detected.

Dependencies are inferred from the claim text.