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US 2012/0068735 A1Published application
Incorporating an independent logic block in a system-on-a-chip
AssigneeIntel Corporation
InventorsDAVID J. HARRIMAN, Daniel S. Froelich
Life of this patent
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Abstract
In one embodiment, the present invention includes a logic having a first link interface to enable communication with an intellectual property (IP) logic adapted on a single semiconductor die with the logic, where the IP logic includes a second link interface coupled to the first link interface via an on-die interconnect. In this way, the IP logic can be unmodified with respect to a standalone device having the IP logic incorporated therein. Other embodiments are described and claimed.
Claims21
An apparatus comprising:
- an upstream logic having a first link interface to enable communication with an intellectual property (IP) logic adapted on a single semiconductor die with the upstream logic, the IP logic including a second link interface coupled to the first link interface via an on-die interconnect, where the IP logic is a downstream component with respect to the upstream logic and unmodified with respect to a standalone device having the IP logic incorporated therein.
A system on a chip (SoC) comprising:
- a first logic having a first link interface modified from a link interface of a Physical Interface for Peripheral Component Interconnect Express™ Architecture (PIPE) specification to emulate functionality of a portion of a physical (PHY) interface of the PIPE specification;
- a second logic coupled to the first logic via an on-die interconnect, the second logic having a second link interface to communicate with the first link interface, wherein the second logic is unmodified with respect to a standalone device having the second logic incorporated therein;
- a PHY interface to enable communication with a component coupled to the SoC by an off-chip interconnect;
- and
- a multiplexer coupled between the first logic, the second logic, and the PHY interface, wherein the multiplexer is controlled to provide a communication from the first link interface to a selected one of the PHY interface and the second link interface.
2 more elements
A method comprising:
- configuring a system-on-a-chip (SoC) including:
- a first logic having a first link interface modified from a link interface of a Physical Interface for Peripheral Component Interconnect Express™ Architecture (PIPE) specification to emulate functionality of a portion of a physical (PHY) interface of the PIPE specification to enable communication via a link-link interface and a link-PHY interface;
- and
- a second logic coupled to the first logic via an on-die interconnect, the second logic having a second link interface to communicate with the first link interface, wherein the second logic is unmodified with respect to a standalone device having the second logic incorporated therein;
- determining if a communication from the first logic is destined to the second logic or to a third logic coupled to the SoC via an off-chip interconnect;
- and
- providing the communication from the first link interface to the PHY interface if the communication is destined to the third logic and providing the communication from the first link interface to the second link interface if the communication is destined to the second logic.
4 more elements
Dependencies are inferred from the claim text.