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US 2012/0068734 A1Published application
Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques
AssigneeQUALCOMM Incorporated
InventorsRajamani Sethuram, Karim Arabi
Life of this patent
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Abstract
Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
Claims35
A circuit, comprising:
- logic circuitry;
- a plurality of scan flip flops coupled to the logic circuitry;
- a plurality of gates coupled between the logic circuitry and the plurality of scan flip flops;
- and
- a control line coupled to a first input of each of the plurality of gates
- each of the plurality of scan flip flops including a q-output coupled to a second input of a corresponding one of the plurality of gates;
- the plurality of gates being configured to output a minimal leakage state vector to the logic circuitry, in response to an enable signal on the control line, and to pass through signals from each of the q-outputs to the logic circuitry in response to absence of the enable signal on the control line.
4 more elements
(canceled)
A circuit, comprising:
- logic circuitry;
- a plurality of scan flip flops coupled to the logic circuitry;
- and
- a control line coupled to a first input of each of the plurality of scan flip flops;
- each of the plurality of scan flip flops including a q-output coupled to a second input of a corresponding one of the plurality of gates;
- the plurality of scan flip flops comprising 0-gated flip flops and 1-gated flip flops configured to output a minimal leakage state vector to the logic circuitry, in response to an enable signal on the control line, and to pass through signals from each of the q-outputs to the logic circuitry in response to absence of the reduce-leakage signal on the control line.
3 more elements
(canceled)
A circuit comprising:
- q-gate logic that holds logic circuitry in a minimum leakage state;
- and
- multiplexer circuitry connected to the q-gate logic that asserts the minimum leakage state for a plurality of operating modes of the circuit.
A circuit comprising:
- means for holding logic circuitry in a minimum leakage state;
- and
- means for asserting the minimum leakage state for a plurality of operating modes of the circuit.
A circuit, comprising:
- a scan path comprising a chain of scan flip flops configured to shift a test vector to circuitry under test, and
- multiplexer circuitry coupled to an input of the scan path, the multiplexer circuitry including an enable input and configured to output a logical ‘0’ to a scan path input upon assertion of the enable input.
A method of generating a minimum leakage state in an integrated circuit design, comprising:
- defining a fault model in an automatic test pattern generator tool in which each fault represents a unique Boolean combination at inputs of a standard cell in the integrated circuit design;
- computing a gain function for each of the faults in which the gain function represents an average leakage power reduction for a corresponding fault;
- sorting the faults in order of the computed gain function for the faults;
- generating a vector set by performing an automatic test pattern generation to detect as many of the faults as possible with vectors of the set;
- and
- selecting a vector of the set in which a summation of gains corresponding to the faults detected by the vector is maximum.
3 more elements
An apparatus for generating a minimum leakage state in an integrated circuit design, comprising:
- means for defining a fault model in an automatic test pattern generator tool in which each fault represents a unique Boolean combination at inputs of a standard cell in the integrated circuit design;
- means for computing a gain function for each of the faults in which the gain function represents an average leakage power reduction for a corresponding fault;
- means for sorting the faults in order of the computed gain function for the faults;
- means for generating a vector set by performing an automatic test pattern generation to detect as many of the faults as possible with vectors of the set;
- and
- means for selecting a vector of the set in which a summation of gains corresponding to the faults detected by the vector is maximum.
3 more elements
A method of generating a minimum leakage state in an integrated circuit design, comprising the steps of:
- defining a fault model in arm automatic test pattern generator tool in which each fault represents a unique Boolean combination at inputs of a standard cell in the integrated circuit design;
- computing a gain function for each of the faults in which the gain function represents an average leakage power reduction for a corresponding fault;
- sorting the faults in order of the computed gain function for the faults;
- generating a vector set by performing an automatic test pattern generation to detect as many of the faults as possible with vectors of the set;
- and
- selecting a vector of the set in which a summation of gains corresponding to the faults detected by the vector is maximum.
3 more elements
A computer program product comprising:
- a computer-readable medium having program code recorded thereon, the program code comprising:
- program code to define a fault model in an automatic test pattern generator tool in which each fault represents a unique Boolean combination at inputs of a standard cell in an integrated circuit design;
- program code to compute a gain function for each of the faults in which the gain function represents an average leakage power reduction for a corresponding fault;
- program code to sort the faults in order of the computed gain function for the faults;
- program code to generate a vector set by performing an automatic test pattern generation to detect as many of the faults as possible with vectors of the set;
- and
- program code to select a vector of the set in which a summation of gains corresponding to the faults detected by the vector is maximum.
4 more elements
A circuit, comprising:
- logic circuitry;
- a plurality of scan flip flops coupled to the logic circuitry;
- and
- means for holding a minimal leakage state of the logic circuitry, the holding means being coupled between the logic circuitry and q-outputs of each of the plurality of scan flip flops.
1 more element
A circuit comprising:
- means for holding logic circuitry in a minimum leakage state;
- and
- means for asserting the minimum leakage state for a plurality of operating modes of the circuit, the asserting means being coupled to the holding means.
A circuit, comprising:
- means for shifting a test vector to circuitry under test, and
- multiplexer circuitry coupled to an input of the shifting means, the multiplexer circuitry including an enable input and configured to output a logical ‘0’ to the input of the shifting means upon assertion of the enable input.
Dependencies are inferred from the claim text.