Eeprom cell with charge loss
AssigneeSTMicroelectronics (Rousset) SAS
InventorPascal Fornara
Life of this patent
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Abstract
An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.
Claims8
An EEPROM cell comprising a dual-gate MOS transistor having its two gates separated by an insulating layer, wherein the insulating layer is formed of a first portion and of a second portion less insulating than the first portion.
A method for forming an EEPROM cell comprising a dual-gate polysilicon transistor, and comprising, after a step of forming of a first gate and before a step of forming of a second gate, the successive steps of:
- forming, on the first gate, a first layer of an insulating material;
- forming, in the first insulating material layer, an opening;
- forming, in said opening and on the first gate, a second insulating material layer (96), the second layer being less insulating than the first insulating layer.
Dependencies are inferred from the claim text.