Stacked chip assembly having vertical vias

A method of forming a stacked microelectronic assembly comprising the steps of:

• (a) stacking a first semiconductor element atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface and separated from a semiconductor layer of the semiconductor element by a dielectric layer, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening and exposing a portion of the dielectric layer adjacent to the respective conductive pad, the first and second openings having respective interior surfaces extending at angles relative to each other, wherein at least the second opening of the first semiconductor element extends through the conductive pad of the first semiconductor element, and the conductive pad of the first semiconductor element overlies the conductive pad of the second semiconductor element;
• and
• (b) forming an electrically conductive element extending through the first and second openings of each of the first and second semiconductor elements, the conductive element conforming to contours of the interior surfaces of the first and second openings and electrically connecting the conductive pads.

An assembly comprising:

• a first semiconductor element stacked atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening at least to the respective conductive pad, the first and second openings having respective interior surfaces extending at angles relative to each other, wherein at least the second opening of the first semiconductor element extends through the conductive pad of the first semiconductor element, and the conductive pad of the first semiconductor element overlies the conductive pad of the second semiconductor element;
• and
• an electrically conductive element extending through the first and second openings of each of the first and second semiconductor elements, the conductive element conforming to contours of the interior surfaces of the first and second openings and electrically connecting the conductive pads.