Non-volatile semiconductor memory device

A non-volatile semiconductor memory device comprising:

• a plurality of memory sub-blocks, each memory sub-block comprising a plurality of memory transistors connected in parallel between a first node and a second node;
• a first select transistor having a first end connected to the first node;
• a second select transistor having a first end connected to the second node;
• a plurality of word-lines connected to respective gates of the memory transistors;
• a bit-line connected to a second end of the first select transistor;
• and
• a source-line connected to a second end of the second select transistor, the memory sub-block comprising:
• a semiconductor substrate;
• a dielectric film formed above the semiconductor substrate;
• a first conductive layer formed in the dielectric film and extending in a first direction perpendicular to the semiconductor substrate, the first conductive layer functioning as the first node;
• a second conductive layer formed in the dielectric film and extending in the first direction, the second conductive layer functioning as the second node;
• a semiconductor layer formed connecting the first conductive layer and the second conductive layer and extending in a second direction in parallel with the semiconductor substrate, the semiconductor layer functioning as a channel layer of the memory transistor;
• and
• a third conductive layer formed as opposed to the semiconductor layer via a gate-insulating film, the third conductive layer functioning as the gate electrode of the memory transistor,
• the gate-insulating film comprising a charge accumulation film as a portion thereof, the gate-insulating film being formed in a closed loop surrounding the third conductive layer in a cross-section in parallel with the first direction and the second direction.

A method of manufacturing a non-volatile semiconductor memory device comprising a plurality of memory sub-blocks, each memory sub-block comprising a plurality of memory transistors connected in parallel between a first node and a second node, the method comprising:

• forming alternately a sacrificial film, a conductive film, and an insulating film on a semiconductor substrate in a plurality of layers, and then patterning the sacrificial films, the conductive films, and the insulating films into a stripe shape having a first direction as the longitudinal direction thereof;
• depositing a dielectric film to have the sacrificial films, the conductive films, and the insulating films embedded therein;
• forming a plurality of through-holes in the dielectric film in a matrix, the through-holes being partially overlapped with the sacrificial films, the conductive films, and the insulating films of the stripe shape;
• etching away the sacrificial films through the through-holes;
• depositing a gate-insulating film of a memory transistor in the through-hole, the gate-insulating film having a thickness that leaves a void in the through-hole, and the gate-insulating film covering the entire peripheries of the conductive films and the insulating films;
• and
• forming a semiconductor layer in the void.