Semiconductor memory device having a floating body capacitor, memory cell array having the same and method of manufacturing the same
AssigneeHynix Semiconductor Inc.
InventorJong Su KIM
Life of this patent
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Abstract
A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven.
Claims17
A semiconductor memory device comprising:
- an SOI substrate with a base substrate on which a conducting surface, a buried insulating layer and a device-forming layer are stacked;
- a switching transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region;
- and
- a storage capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer,
- wherein the storage capacitor is electrically connected between a body of the switching transistor and a bias line, and charged or discharged in response to a driving of the switching transistor.
A method for forming a semiconductor memory device comprising:
- providing an SOI substrate, wherein the SOI substrate includes a base substrate having a conducting surface, a buried insulating layer and a device-forming layer;
- forming a transistor having a gate, a source region and a drain region on the SOI substrate;
- and
- forming a contact plug in contact with the conducting surface of the base substrate, wherein sidewalls of the contact plug are contacted with an active area of the device-forming layer, and an adjustable bias voltage is applied to the contact plug,
- wherein a parasitic capacitor is formed in the SOI substrate by connecting between the conducting surface and the active area, as a storage capacitor.
A memory cell array of the semiconductor memory device comprising:
- a plurality of word lines;
- a plurality of bit lines arranged to intersect with the plurality of the word lines, respectively;
- and
- a plurality of memory cells formed in respective points of intersection of the plurality of word lines with the plurality of bit lines, respectively;
- wherein one of the memory cells includes a switching transistor connected between one of the word lines and one of the bit lines and a storage capacitor connected between a body of the switching transistor and a bias line.
Dependencies are inferred from the claim text.