Semiconductor device and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsTatsuya Ishida, Masahiro Inohara
Life of this patent
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Abstract
According to embodiments, there is provided a semiconductor device, including: a logic circuit; an interlayer insulating film formed above the logic circuit; an amorphous silicon layer including: a non-silicide layer formed on the interlayer insulating film; and a silicide layer formed on the non-silicide layer; a TFT formed on the amorphous silicon layer; and a contact plug formed to plug a through hole penetrating the interlayer insulating film, the contact plug being electrically connected to the logic circuit, an upper part of the contact plug being connected to the silicide layer.
Claims14
A semiconductor device, comprising:
- a logic circuit;
- an interlayer insulating film formed above the logic circuit;
- an amorphous silicon layer comprising:
- a non-silicide layer formed on the interlayer insulating film;
- and
- a silicide layer formed on the non-silicide layer;
- a TFT formed on the amorphous silicon layer;
- and
- a contact plug formed to plug a through hole penetrating the interlayer insulating film, the contact plug being electrically connected to the logic circuit, an upper part of the contact plug being connected to the silicide layer.
A semiconductor device manufacturing method, comprising:
- forming a contact plug in a through hole that is formed in an interlayer insulating film provided on a logic circuit;
- etching the interlayer insulating film by a predetermined thickness;
- forming an amorphous silicon layer on the interlayer insulating film and on the contact plug;
- and
- siliciding the amorphous silicon layer from a top-part thereof to a predetermined depth.
A semiconductor device manufacturing method, comprising:
- forming a contact plug in a through hole that is formed in an interlayer insulating film provided on a logic circuit;
- forming an amorphous silicon layer on the interlayer insulating film and on the contact plug;
- selectively etching the amorphous silicon layer on the contact plug to a predetermined height;
- and
- siliciding the amorphous silicon layer from a top-part thereof to a predetermined depth.
A semiconductor device manufacturing method, comprising:
- forming a contact plug in a through hole that is formed in an interlayer insulating film provided on a logic circuit;
- selectively forming a metal layer on a top-part of the contact plug;
- forming an amorphous silicon layer on the interlayer insulating film and on the contact plug;
- and
- siliciding the amorphous silicon layer from a top-part thereof to a predetermined depth.
Dependencies are inferred from the claim text.