Nanowire Field Effect Transistors

A method for forming a nanowire field effect transistor (FET) device, the method comprising:

• forming a raised silicon on insulator (SOI) region on a semiconductor substrate;
• patterning a first hardmask layer over a first portion of the SOI region and a second portion of the SOI region;
• forming from an exposed portion of the SOI region, a first suspended nanowire over the semiconductor substrate;
• forming a first gate structure around a portion of the first suspended nanowire;
• patterning a second hardmask layer over the first gate structure and the first suspended nanowire;
• removing the first hardmask layer to expose the first and second portions of the SOI region;
• forming, from the exposed first SOI portion, a second suspended nanowire over the semiconductor substrate and from the exposed second SOI portion, a third suspended nanowire over the semiconductor substrate;
• forming a second gate structure around a portion of the second suspended nanowire and a third gate structure around a portion of the third suspended nanowire;
• and
• removing the second hardmask layer.