Nonvolatile memory element and fabrication method for nonvolatile memory element

A nonvolatile memory element comprising:

• a substrate;
• a lower electrode layer formed on said substrate;
• a first variable resistance layer formed on said lower electrode layer and comprising a metal oxide;
• a second variable resistance layer formed on said first variable resistance layer and comprising a metal oxide having smaller oxygen deficiency than oxygen deficiency of said first variable resistance layer;
• an upper electrode layer formed on said second variable resistance layer;
• an interlayer insulating layer formed to cover at least side surfaces of said lower electrode layer, said first variable resistance layer, and said second variable resistance layer;
• a stress buffering region layer for buffering a stress on said upper electrode layer, said stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of said upper electrode layer and having a stress smaller than a stress of an insulating layer used as said interlayer insulating layer;
• a contact extending to said upper electrode layer;
• and
• a wiring pattern connected to said contact, and
• said stress buffering region layer is an insulating layer having porous structure.

A nonvolatile memory element comprising:

• a substrate;
• a lower electrode layer formed on said substrate;
• a first variable resistance layer formed on said lower electrode layer and comprising a metal oxide;
• a second variable resistance layer formed on said first variable resistance layer and comprising a metal oxide having smaller oxygen deficiency than oxygen deficiency of said first variable resistance layer;
• an upper electrode layer formed on said second variable resistance layer;
• an interlayer insulating layer formed to cover at least side surfaces of said lower electrode layer, said first variable resistance layer, and said second variable resistance layer;
• a stress buffering region layer for buffering a stress on said upper electrode layer, said stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of said upper electrode layer and having a stress smaller than a stress of an insulating layer used as said interlayer insulating layer;
• a contact extending to said upper electrode layer;
• and
• a wiring pattern connected to said contact, and
• said stress buffering region layer is an air layer.

A fabrication method for a nonvolatile memory element, comprising:

• a first process of forming a lower electrode on a substrate;
• a second process of forming a first variable resistance layer comprising a metal oxide on the lower electrode layer;
• a third process of forming, on the first variable resistance layer, a second variable resistance layer comprising a metal oxide having smaller oxygen deficiency than oxygen deficiency of the first variable resistance layer;
• a fourth process of forming an upper electrode layer on the second variable resistance layer;
• a fifth process of forming a stress buffering region layer for buffering a stress on the upper electrode layer, the stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of the upper electrode layer;
• a sixth process of forming an interlayer insulating layer to cover at least side surfaces of the lower electrode layer, the first variable resistance layer, and the second variable resistance layer;
• a seventh process of forming a contact extending to the upper electrode layer;
• and
• an eighth process of forming a wiring pattern connected to the contact,
• wherein, in said fifth process, the stress buffering layer is formed using an insulating layer having a stress smaller than an insulating layer used as the interlayer insulating layer having porous structure.

A fabrication method for a nonvolatile memory element, comprising:

• a first process of forming a lower electrode on a substrate;
• a second process of forming a first variable resistance layer comprising a metal oxide on the lower electrode layer;
• a third process of forming, on the first variable resistance layer, a second variable resistance layer comprising a metal oxide having smaller oxygen deficiency than oxygen deficiency of the first variable resistance layer;
• a fourth process of forming an upper electrode layer on the second variable resistance layer;
• a fifth process of forming a stress buffering region layer for buffering a stress on the upper electrode layer, the stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of the upper electrode layer;
• a sixth process of forming an interlayer insulating layer to cover at least side surfaces of the lower electrode layer, the first variable resistance layer, and the second variable resistance layer;
• a seventh process of forming a contact extending to the upper electrode layer;
• and
• an eighth process of forming a wiring pattern connected to the contact,
• wherein, in said fifth process, the stress buffering layer is formed as an air layer having a stress smaller than an insulating layer used as the interlayer insulating layer.