Memory Arrays And Methods Of Forming Memory Cells

A method of forming a plurality of memory cells, comprising:

• forming first conductive lines within first trenches in a first dielectric material;
• the first trenches extending along a first axis;
• forming second dielectric material over the first dielectric material, and patterning the second dielectric material to have openings extending therethrough to the first conductive lines;
• forming memory cells within the openings, each of the memory cells comprising programmable material sandwiched between top and bottom electrodes;
• the programmable material comprising a high k dielectric portion directly against a multivalent metal oxide portion;
• forming a third dielectric material over the second dielectric material and patterning the third dielectric material to have second trenches over the memory cells, the second trenches extending along a second axis which intersects the first axis;
• and
• forming second conductive lines within the second trenches.

A method of forming a plurality of memory cells, comprising:

• forming first conductive lines extending along a first axis;
• forming spaced-apart bottom electrodes along each of the conductive lines;
• forming programmable material over and in direct contact with the bottom electrodes;
• the programmable material comprising a high k dielectric portion directly against a multivalent metal oxide portion;
• forming top electrode material over and directly against the high k dielectric portion of the programmable material;
• forming patterned electrically conductive hard mask material over the top electrode material;
• the patterned hard mask material comprising masking lines extending along a second axis which is substantially perpendicular to the first axis;
• transferring a pattern from the patterned electrically conductive hard mask material into the top electrode material to pattern the top electrode material into lines;
• the programmable material comprising cell regions directly between top electrode material lines and bottom the electrodes, and comprising intervening regions between the cell regions;
• and
• forming second conductive lines directly over the masking lines, the second conductive lines extending along the second axis.

A method of forming a plurality of memory cells, comprising:

• forming a first conductive line within a first trench in a first dielectric material;
• the first trench extending along a first axis;
• forming second dielectric material over the first dielectric material, and patterning the second dielectric material to have openings extending therethrough to the first conductive line;
• forming bottom electrode material along bottoms of the openings:
• forming multivalent metal oxide within the openings over the bottom electrode material, the multivalent metal oxide and bottom electrode material together forming a plurality of memory cell plugs;
• forming an expanse of high k dielectric material that extends across the memory cell plugs;
• forming a protective layer over the high k dielectric material;
• forming a third dielectric material over the protective layer and patterning the third dielectric material to have second trenches over the protective layer, the second trenches extending along a second axis which intersects the first axis;
• extending the second trenches through the protective layer to an upper surface of the high k dielectric material;
• forming top electrode material within bottoms of the second trenches;
• and
• forming second conductive lines over the top electrode material within the second trenches.

A method of forming a plurality of memory cells, comprising:

• forming a first conductive line extending along a first axis;
• forming first electrode material along the first conductive line;
• forming an expanse of first programmable material over and in direct contact with the first electrode material;
• the first programmable material comprising a first high k dielectric portion over and directly against a first multivalent metal oxide portion;
• forming second electrode material over the first programmable material;
• forming patterned electrically conductive hard mask material over the second electrode material;
• the patterned hard mask material comprising spaced-apart masking features;
• transferring a pattern from the patterned electrically conductive hard mask material into the second electrode material;
• the patterned second electrode material comprising spaced-apart segments;
• the first programmable material comprising first cell regions directly beneath the second electrode material segments, and comprising first intervening regions between the first cell regions;
• forming electrically conductive structures over the masking features of the electrically conductive hard mask material;
• the electrically conductive structures including second conductive lines that extend along a second axis which is substantially perpendicular to the first axis;
• the electrically conductive structures having upper pedestals, the upper pedestals having caps corresponding to third electrodes;
• forming an expanse of second programmable material over and in direct contact with the third electrode caps;
• the second programmable material comprising a second multivalent metal oxide portion over and directly against a second high k dielectric portion;
• forming fourth electrodes over and directly against the second programmable material;
• the second programmable material comprising second cell regions directly beneath the fourth electrodes, and comprising second intervening regions between the second cell regions, and
• forming a third conductive line extending across the fourth electrodes.

An array of memory cells, comprising:

• a plurality of first conductive lines extending along a first axis;
• spaced-apart programmable material lines extending across the first conductive lines;
• each of the programmable material lines comprising a high k dielectric portion directly against a multivalent metal oxide portion;
• the programmable material lines extending along a second axis which intersects the first axis;
• spaced-apart segments of first electrode material over the first conductive lines;
• the multivalent metal oxide of the programmable material lines being directly against the segments of the first electrode material;
• lines of second electrode material over and directly against the high k dielectric portions of the programmable material lines;
• and
• a plurality of second conductive lines extending along the first axis and being directly against the second electrode material.

An array of memory cells, comprising:

• first conductive lines extending along a first axis;
• first electrode material along the first conductive lines;
• an expanse first programmable material over and in direct contact with the first electrode material;
• the expanse of first programmable material extending across a plurality of the first conductive lines;
• the first programmable material comprising a first high k dielectric portion over and directly against a first multivalent metal oxide portion;
• spaced-apart electrically conductive structures over the first programmable material, the electrically structures having bottom portions that include conductive pedestals containing bases of second electrode material that are directly against the first high k dielectric portion;
• the first programmable material comprising first cell regions directly beneath the second electrode material bases, and comprising first intervening regions between the first cell regions;
• the electrically conductive structures including second conductive lines that extend along a second axis which is substantially perpendicular to the first axis;
• the electrically conductive structures having upper pedestals, the upper pedestals having caps corresponding to third electrodes;
• an expanse of second programmable material over and in direct contact with the third electrode caps;
• the expanse of second programmable material extending across a plurality of the third electrode caps;
• the second programmable material comprising a second multivalent metal oxide portion over and directly against a second high k dielectric portion;
• fourth electrodes directly against the second programmable material;
• the second programmable material comprising second cell regions directly beneath the fourth electrodes, and comprising second intervening regions between the second cell regions;
• and
• third conductive lines extending across the fourth electrodes, the third conductive lines extending along the first axis.