Design supporting method, design supporting device, computer product, and semiconductor integrated circuit

A design supporting device comprising:

• a detecting unit that detects, from layout data, a clock path that propagates a clock signal from a clock source and of which clock buffers are single-gate inverting clock buffers;
• a selecting unit that sequentially selects the data holding elements connected to the clock path detected by the detecting unit;
• an identifying unit that identifies an input clock buffer of the data holding element, each time a data holding element is selected by the selecting unit;
• a determining unit that based on a number of gates from the clock source to the clock buffer, determines whether the clock buffer identified by the identifying unit outputs the clock signal from the clock source according to non-inverting logic or inverting logic;
• a replacing unit that based on a determination result obtained by the determining unit, replaces the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal;
• and
• an output unit that outputs a replacement result obtained by the replacing unit.

A computer-readable medium storing therein a design supporting program for designing a semiconductor integrated circuit that includes a plurality of data holding elements and a clock path that propagates a clock signal from a clock source to the data holding elements, the design supporting program causing a computer to execute a process comprising:

• detecting, from layout data of the semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers;
• selecting sequentially the data holding elements connected to the clock path detected at the detecting;
• identifying an input clock buffer of the data holding element, each time a data holding element is selected at the selecting;
• determining, based on a number of gates from the clock source to the clock buffer, whether the clock buffer identified at the identifying outputs the clock signal from the clock source according to non-inverting logic or inverting logic;
• replacing, based on a result of the determining, the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal;
• and
• outputting a result obtained at the replacing.