Annotation of RTL to Simplify Timing Analysis
OwnerManjeri R. Krishnaninventor
Life of this patent
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Abstract
A method for simulating operation of a design model for a digital system is provided. A library of functional cells is maintained in a storage unit that includes an attribute template with one or more of the functional cells in the library. The attribute template provides fields for specifying design constraint data for a functional cell each time it is instantiated in a design model. A design model is created and stored that includes one or more instantiations of a functional cell and its associated design constraint data. A set of test cases may be pruned to remove test cases that are not needed based on the design constraint data associated with the instantiated functional cells of the design model.
Claims14
A method for simulating operation of a design model for a digital system, the method comprising:
- storing a library of functional cells in a storage unit;
- including an attribute template with one or more of the functional cells in the library, wherein the attribute template provides fields for specifying design constraint data for a functional cell each time it is instantiated in a design model;
- and
- storing a design model in a storage unit that includes one or more instantiations of a functional cell and its associated design constraint data.
A design analysis system for simulating the operation of a design model for a digital system, the timing analysis system comprising:
- a timing path module configured to receive a high level language design model for the digital system and to determine a set of timing paths for the design model, wherein the design model includes constraint data associated with a specific cell instantiation in the design model;
- and
- a pruning module configured to analyze the constraint data and to prune the set timing paths to indicate timing paths that are not needed based on the constraint data.
An application specific integrated circuit (ASIC) designed by a process, wherein the process comprises:
- creating a high level language design model of one or more logic modules within the ASIC by instantiating functional cells from a library of functional cells;
- and
- capturing design constraint data associated with specific functional cell instantiations while the design model is being created.
Dependencies are inferred from the claim text.