Soft error verification in hardware designs
AssigneeInternational Business Machines Corporation
InventorsSharon Keidar-Barner, Ohad Shacham, Karen Frida Yorav
Life of this patent
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Abstract
Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states.
Claims23
A method for detecting an error in a design that may be caused due to a soft error, the method comprising:
- obtaining the design, wherein the design comprising a plurality of variables and a transition relation from a state to a next state based on at least one input signal;
- computing a set of states of the design in respect to a variable of the plurality of variables, wherein for each state of the set of states, in case a value of the variable is changed due to the soft error, there exists one or more consecutive values to the at least one input signal that result in an error in the design;
- synthesizing a target identification logic configured to detect if a current state of the design is comprised by the set of states;
- simulating the design and the target identification logic, wherein said simulating is performed by a processor;
- said simulating comprising in response to a detection by the target identification logic, changing a value of the variable to simulate the soft error;
- and
- determining whether the error in the design occurred during said simulating.
A computerized apparatus for detecting an error in a design that may be caused due to a soft error, the computerized apparatus having a processor and a storage device;
- the computerized apparatus comprising:
- a design obtainer operative to obtain the design, wherein the design comprising a plurality of variables and a transition relation from a state to a next state based on at least one input signal;
- a target definer configured to determine a set of states of the design in respect to a variable of the plurality of variables, wherein for each state of the set of states, in case a value of the variable is changed due to the soft error, there exists one or more consecutive values to the at least one input signal that result in an error in the design;
- a target identification logic synthesizer configured to synthesize a target identification logic configured to detect if a current state of the design is comprised by the set of states determined by said target definer;
- a simulator configured to simulate operation of the design and the target identification logic synthesized by said target identification logic synthesizer;
- wherein said simulator is operately coupled to a soft error triggering module, said soft error triggering module is configured to change a value of the variable associated with the target identification logic in response to a determination by the target identification logic during simulation that the current state is comprised by the set of states;
- and
- wherein said simulator is operately coupled to an error identification module, said error identification module is configured to indicate whether there is an error in the design based on simulated states of the design.
A computer program product for detecting an error in a design that may be caused due to a soft error, said computer program product comprising:
- a computer readable medium;
- a first program instruction operative to obtain the design, wherein the design comprising a plurality of variables and a transition relation from a state to a next state based on at least one input signal;
- a second program instruction operative to compute a set of states of the design in respect to a variable of the plurality of variables, wherein for each state of the set of states, in case a value of the variable is changed due to the soft error, there exists one or more consecutive values to the at least one input is signal that result in an error in the design;
- a third program instruction operative to synthesize a target identification logic configured to detect if a current state of the design is comprised by the set of states;
- a fourth program instruction operative to simulate the design and the target identification logic, the fourth program instruction is further operative to change a value of the variable to simulate the soft error in response to a detection by the target identification logic during simulation;
- a fifth program instruction operative to determine whether the error in the design occurred during said simulating;
- and
- wherein said first, second, third, fourth and fifth program instructions are stored on said computer readable media.
Dependencies are inferred from the claim text.