Reduction operation device, a processor, and a computer system

A processor comprising:

• a processing unit;
• and
• a reduction operation device that is inputted a plurality of synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and each transmission destinations of the plurality of inputted data corresponding to a next stage of a reduction operation and executes the reduction operation to the inputted data,
• wherein the reduction device comprising:
• a synchronization unit that waits inputs of the plurality of synchronization signals and instruction of the reduction operation to the plurality of inputted data, outputs an arithmetic result of the reduction operation and a transmission destination of the plurality of synchronization signals to m (m>1 and m is integer) number of transmission destinations after a synchronization between the plurality of synchronization signals is established;
• an arithmetic unit that executes an arithmetic operation between n (n>1 and m is integer) number of the inputted data that the synchronization is established;
• a storage unit that stores data and an arithmetic result;
• a transmission unit that transmits the plurality of inputted data and the plurality of synchronization signals to the transmission destination designated by the synchronization unit;
• and
• a reception unit that sends the plurality of synchronization signals and the plurality of transmission destinations to the synchronization unit and the plurality of inputted data to the storage unit,
• wherein the synchronization unit receives the plurality of synchronization signals and at least one of an operation type and a data type included in the inputted instruction of the reduction operation, compares between n number of the operation type or the data type after the synchronization is established, transmits a signal indicating non-correspondence instead of the arithmetic result to m number of transmission destination when the n number of the operation type or the data type do not match, and executes the instruction of the reduction operation when n number of the operation type or the data type match.

A computer system comprising:

• a plurality of processor that are connected through a network, each processor comprises:
• a processing unit;
• and
• a reduction operation device that is inputted a plurality of synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and each transmission destinations of the plurality of inputted data corresponding to a next stage of a reduction operation and executes the reduction operation to the inputted data,
• wherein the reduction operation device comprising:
• a synchronization unit that waits inputs of the plurality of synchronization signals and instruction of the reduction operation to the plurality of inputted data, outputs an arithmetic result of the reduction operation and a transmission destination of the plurality of synchronization signals to m (m>1 and m is integer) number of transmission destinations after a synchronization between the plurality of synchronization signals is established;
• an arithmetic unit that executes an arithmetic operation between n (n>1 and m is integer) number of the inputted data that the synchronization is established;
• a storage unit that stores data and an arithmetic result;
• a transmission unit that transmits the plurality of inputted data and the plurality of synchronization signals to the transmission destination designated by the synchronization unit;
• and
• a reception unit that sends the plurality of synchronization signals and the plurality of transmission destinations to the synchronization unit and the plurality of inputted data to the storage unit,
• wherein the synchronization unit receives the plurality of synchronization signals and at least one of an operation type and a data type included in the inputted instruction of the reduction operation, compares between n number of the operation type or the data type after the synchronization is established, transmits a signal indicating non-correspondence instead of the arithmetic result to m number of transmission destination when the n number of the operation type or the data type do not match, and executes the instruction of the reduction operation when n number of the operation type or the data type match.