US 2012/0060016 A1 · Vector Loads from Scattered Memory Locations

Abstract

Mechanisms for performing a scattered load operation are provided. With these mechanisms, a gather instruction is receive in a logic unit of a processor, the gather instruction specifying a plurality of addresses in a memory from which data is to be loaded into a target vector register of the processor. A plurality of separate load instructions for loading the data from the plurality of addresses in the memory are automatically generated within the logic unit. The plurality of separate load instructions are sent, from the logic unit, to one or more load/store units of the processor. The data corresponding to the plurality of addresses is gathered in a buffer of the processor. The logic unit then writes data stored in the buffer to the target vector register.

Claims20

Dependent claims

A method, in a logic unit of a processor, for performing a load operation into a target vector register, comprising:

receiving, in the logic unit of the processor, a gather instruction specifying a plurality of addresses in a memory from which data is to be loaded into the target vector register of the processor;
automatically generating, within the logic unit of the processor, a plurality of separate load instructions for loading the data from the plurality of addresses in the memory based on the gather instruction;
sending, from the logic unit within the processor, the plurality of separate load instructions to one or more load/store units of the processor;
gathering, within the logic unit of the processor, the data corresponding to the plurality of addresses in a buffer of the processor;
and
writing, by the logic unit of the processor, data stored in the buffer to the target vector register.

3 more elements

Dependencies are inferred from the claim text.

Vector Loads from Scattered Memory Locations

Life of this patent

Vector Loads from Scattered Memory Locations

Life of this patent

Abstract

Claims20