Vector Loads with Multiple Vector Elements from a Same Cache Line in a Scattered Load Operation

An apparatus, comprising:

• a cache memory array;
• a cache line buffer coupled to the cache memory array;
• and
• a plurality of data element selector logic units coupled to the cache line buffer, wherein the apparatus is configured to:
• receive an extended address, the extended address having a base address portion and a plurality of data element address portions that specifies a plurality of data elements to be accessed using the single extended address;
• provide each of the plurality of data element address portions to a corresponding data element selector logic unit in the plurality of data element selector logic units;
• select, by each data element selector logic unit, a corresponding data element from the cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit;
• and
• output, by each data element selector logic unit, the corresponding data element.

A processor, comprising:

• a cache memory unit comprising a plurality of data element selector logic units and a cache line buffer;
• and
• a load/store unit coupled to the cache memory unit, wherein the processor is configured to:
• receive an extended address in the cache memory unit, the extended address having a base address portion and a plurality of data element address portions that specifies a plurality of data elements to be accessed using the single extended address;
• provide each of the plurality of data element address portions to a corresponding data element selector logic unit in the plurality of data element selector logic units of the cache memory unit;
• select, by each data element selector logic unit, a corresponding data element from the cache line buffer of the cache memory unit based on a corresponding data element address portion provided to the data element selector logic unit;
• and
• output, by each data element selector logic unit, the corresponding data element.