Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy

A memory system having a plurality of cache levels comprising:

• means for storing in a lower level cache a plurality of first cache lines each with an allocation bit, each allocation bit indicating whether one of the plurality of first cache lines associated with the allocation bit was allocated in a next higher level cache;
• and
• means for determining whether a first cache line selected for displacement from the plurality of first cache lines is a cache line that is redundant with a cache line in the next higher level cache based on an allocation bit associated with the selected first cache line in response to a memory access having a fetch address hit in the next higher level cache, to avoid a castout of the selected first cache line to the next higher level cache in response to the allocation bit of the selected first cache line that indicates the selected first cache line is redundant with a cache line in the next higher level cache, and to castout the selected first cache line to the next higher level cache, based on the allocation bit indicating the selected first cache line is not present in the next higher level cache for the access having the fetch address hit in the next higher level cache, wherein a cache line and an associated allocation bit are stored in the lower level cache for the access having the fetch address hit in the next higher level cache, the associated allocation bit signifies the cache line is present in the next higher level cache.

A computer readable non-transitory medium encoded with computer readable program data and code, the program data and code when executed operable to:

• access a selected line to be displaced in a lower level cache in response to a memory access having a fetch address hit in a next higher level cache;
• identify information associated with the selected line which indicates that the selected line is not present in the next higher level cache;
• and
• allocate, for the memory access having the fetch address hit in the next higher level cache, the selected line in response to the identified information at an address in the next higher level cache determined by a least recently used replacement policy of the next higher level cache.