Semiconductor memory device

A semiconductor package comprising:

• a package interface including at least a first pair of terminals,
• a stack of semiconductor chips;
• a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip;
• and
• an interface circuit including an input connected to the first pair of terminals to receive a differential input signal providing first information, and including an output to provide a differential output signal including the first information in a differential signal format to at least one of the plurality of stacks of through substrate vias.

A semiconductor package comprising:

• a package interface including at least a first pair of terminals,
• a stack of semiconductor chips;
• a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip;
• and
• an interface circuit including an input connected to the first pair of terminals to receive a differential input signal providing first information, and including an output to provide an output signal including the first information to at least one of the plurality of stacks of through substrate vias,
• wherein the interface circuit is configured to interpret the differential input signal as a multi-level signal, and to provide the output signal based on the interpreted multi-level signal.

A semiconductor package comprising:

• package terminals connectable to an address bus;
• a stack of memory chips;
• an interface circuit, comprising:
• an address buffer connected to the package terminals to receive an external address,
• an address translation circuit connected to receive the external address from the address buffer, and having an output of an internal address, and
• a monitoring circuit configured to monitor an amount of access operations to at least one memory location of the stack of memory chips and provide a corresponding monitoring result;
• and
• a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the memory chips of the stack, each through substrate via electrically connected to a through substrate via of a immediately adjacent memory chip, each stack of through substrate vias connected to receive the internal address at the output of the address translation circuit;
• wherein the address translation circuit is configured to translate the external address to an internal address in response to at least the monitoring result of the monitoring circuit.

A semiconductor package comprising:

• package terminals;
• a stack of memory chips;
• an interface circuit, comprising:
• an address buffer connected to the package terminals to receive an external address, and
• an address translation circuit connected to receive the external address from the address buffer, and having an output that outputs an internal address;
• a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the memory chips each electrically connected to a through substrate via of an immediately adjacent memory chip, each stack of the plurality of stacks of through substrate vias connected to receive an internal address at the output of the address translation circuit;
• and
• the interface circuit comprising a refresh controller in logical communication with the package terminals and configured to receive an external refresh control signal, the refresh controller operable to output a series of internal refresh control signals, each of the series of internal refresh control signals operable to initiate a memory refresh of different parts of the stack of memory chips.

A semiconductor package comprising:

• a package interface including package terminals including at least a first pair of terminals,
• a stack of memory chips;
• a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the memory chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent memory chip;
• and
• an interface circuit including:
• an input connected to the first pair of terminals to receive a differential signal providing first information, and including an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias
• an address buffer connected to a plurality of the package terminals to receive an external address,
• an address translation circuit connected to receive the external address from the address buffer, and having an output of an internal address,
• a monitoring circuit configured to monitor an amount of access operations to at least one memory location of the stack of memory chips and provide a corresponding monitoring result, and
• a refresh controller in logical communication with a plurality of the package terminals and configured to receive an external refresh control signal, the refresh controller operable to output a series of internal refresh control signals, each of the series of internal refresh control signals operable to initiate a memory refresh of different parts of the stack of memory chips,
• wherein the address translation circuit is configured to translate the external address to an internal address in response to at least the monitoring result of the monitoring circuit.