Processor independent loop entry cache
AssigneeAtmel Rousset S.A.S.
InventorsFranck Lunadier, Frédéric Schumacher
Life of this patent
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Abstract
A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.
Claims20
A system comprising a memory controller, wherein the memory controller is configured to receive read requests from a processor and return memory words from memory, and wherein the memory controller comprises:
- an address comparator configured to determine a difference between a previous read request address and a current read request address and to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump;
- and
- a loop entry cache configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.
A method performed by a memory controller, the method comprising:
- receiving from a processor a previous read request address and a current read request address for memory words in memory;
- determining a difference between the previous read request address and the current read request address;
- determining that the difference is positive and less than a certain address difference;
- and
- storing a current memory word from the memory for the current read request address in a loop entry cache.
Dependencies are inferred from the claim text.