Precision synchronisation architecture for superspeed universal serial bus devices

A method of providing a synchronisation channel to a SuperSpeed USB device, comprising:

• establishing a SuperSpeed communication channel connection to said SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point;
• multiplexing synchronization information onto said D+/D− data signalling lines at the upstream connection point;
• and
• demultiplexing the synchronization information from said D+/D− signalling lines at a downstream connection point of the cable;
• whereby said synchronisation channel is maintained across the D+/D− data signalling lines.

A USB device, comprising:

• first circuitry adapted to perform at least one SuperSpeed USB device function;
• second circuitry adapted to perform at least one non-SuperSpeed USB device function;
• a local clock;
• synchroniser circuitry;
• and
• multiplexing circuitry for placing the second circuitry and upstream non-SuperSpeed USB D+/D− data signalling lines of the USB device in data communication, and operable to selectively connect and disconnect the synchroniser circuitry and the non-SuperSpeed USB D+/D− data signalling lines;
• wherein the USB device is enabled as a synchronised USB device when the synchroniser circuitry and the non-SuperSpeed USB D+/D− data signalling lines are connected by the multiplexing circuitry so that the local clock can be synchronised to information contained in the signals carried by the non-SuperSpeed USB D+/D− data signalling lines.

An apparatus for synchronising a plurality of attached SuperSpeed USB devices, the apparatus comprising:

• circuitry adapted to perform a SuperSpeed USB Hub function, said circuitry providing an upstream port and a plurality of downstream ports;
• circuitry adapted to perform a non-SuperSpeed USB Hub function said circuitry providing an upstream port and a plurality of downstream ports;
• synchroniser circuitry comprising a local clock, and adapted to generate synchronization information, said synchronization information comprising clock signals, a notion of time and trigger signals;
• circuitry adapted to observe both said SuperSpeed and non-SuperSpeed upstream ports and to lock said local clock to a data structure contained on said upstream port;
• a respective multiplexer for each downstream port of said USB Hub function circuitry, said plurality of multiplexers adapted to multiplex either signals from said non-SuperSpeed USB Hub function or from said synchroniser onto said each of said plurality of downstream ports of said apparatus;
• and
• controller circuitry adapted to control the state of said plurality of multiplexers;
• wherein said controller circuitry is adapted to control said plurality of multiplexers to connect either said non-SuperSpeed Hub function downstream ports or said synchroniser output to said respective downstream ports of said apparatus.