System and method for a hierarchical buffer system for a shared data bus

Abstract

The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing.

Dependencies are inferred from the claim text.