Method and apparatus for performing floating-point division

A method comprising:

• processing a floating-point division fix-up instruction;
• and
• based on the processed floating-point division fix-up instruction, causing input check/output correction floating-point division logic to:
• examine a first input representing a numerator and a second input representing a denominator of the input check/output correction floating-point division logic to determine whether a special case of floating-point division occurs;
• and
• provide an output representing a floating-point division result of the input check/output correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input check/output correction floating-point division logic.

An apparatus comprising:

• a floating-point arithmetic logic unit (ALU) comprising input check/output correction floating-point division logic responsive to a floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to:
• examine a first input representing a numerator and a second input representing a denominator of the input check/output correction floating-point division logic to determine whether a special case of floating-point division occurs;
• and
• provide an output representing a floating-point division result of the input check/output correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input check/output correction floating-point division logic;
• and
• wherein the apparatus is operative to generate at least a portion of the image based on the output representing the floating-point division result of the input check/output correction floating-point division logic.

A computer readable medium storing instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit comprising a processor comprising:

• a floating-point arithmetic logic unit (ALU) comprising input check/output correction floating-point division logic responsive to a floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to:
• examine a first input representing a numerator and a second input representing a denominator of the input check/output correction floating-point division logic to determine whether a special case of floating-point division occurs;
• and
• provide an output representing a floating-point division result of the input check/output correction floating-point division logic based on the determined special case of floating-point division and a third input representing a candidate quotient of the input check/output correction floating-point division logic.