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AssigneeNEC Corporation
InventorKAZUHIRO KASHIWAKURA
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Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD−Z1si[i]×VDD/(Z1si[i]+Z11[i]),where Z1si[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Z1si[i]+Z11[i])/(Z1si[i]−Z11[i]) satisfies |Vr[i]|≦Δ V (power supply variation tolerance range).
A method of verifying design validity of an electronic circuit board on which a semiconductor device is mounted, the method comprising:
An apparatus for verifying design validity of an electronic circuit board on which a semiconductor device is mounted, the apparatus comprising:
A program causing a computer to execute processing for verifying design validity of an electronic circuit board on which a semiconductor device is mounted, the processing comprising:
Dependencies are inferred from the claim text.