System and method for communication handshaking between processors
AssigneeIntegrated Device Technology, Inc.
InventorDETELIN MARTCHOVSKY
Life of this patent
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Abstract
System and method for handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor are described. In one embodiment, the method comprises the first processor disabling an interrupt function on the first pin; and, subsequent to the disabling, interrupting the second processor by driving the first pin to a first logic level and then releasing the first pin to a second logic level.
Claims19
A method for handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor, the method comprising:
- the first processor:
- disabling an interrupt function on the first pin;
- and
- subsequent to the disabling, interrupting the second processor by driving the first pin to a first logic level and then releasing the first pin to a second logic level.
A method for enabling handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor, the method comprising:
- the first processor:
- preparing a message to be sent to the second processor;
- enabling a slave communication interface of the first processor;
- disabling an interrupt function on the first pin;
- and
- driving the first pin to a first logic level to interrupt the second processor.
The method of claim 12 wherein the first and second pins are each general purpose input/output (“GPIO”) pins.
The method of claim 12 wherein each of the pins is in open configuration and has interrupt capability.
A communications system for enabling handshaking between processors via a single wire, the communications system comprising:
- a first processor having a first input/output pin;
- a second processor having a second input/output pin connected to the first input/output pin of the first processor;
- a communications interface between the first and second processors;
- wherein all handshaking functions occur only via the first and second pins.
Dependencies are inferred from the claim text.