Method of Forming Shielded Gate Power Transistor Utilizing Chemical Mechanical Planarization
AssigneeFairchild Semiconductor Corporation
InventorsBruce Douglas Marchant, Thomas E. Grebs, Rodney S. Ridley, Nathan Lawrence Kraft
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Abstract
A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
Claims16
1-57. (canceled)
A method of forming a shielded gate field effect transistor comprising:
- forming a plurality of active gate trenches in a silicon region;
- lining lower sidewalls and bottom of the active gate trenches with a shield dielectric;
- using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon;
- forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches;
- lining upper sidewalls of the active gate trenches with a gate dielectric;
- and
- forming a gate electrode over the IPD in an upper portion of the active gate trenches.
72-106. (canceled)
Dependencies are inferred from the claim text.