Pre-metal deposition clean process

A process of forming an integrated circuit, comprising:

• providing a semiconductor substrate;
• forming a metal oxide semiconductor (MOS) transistor in and on said substrate, by a process including:
• forming an MOS gate dielectric layer on a top surface of said substrate;
• forming an MOS gate on a top surface of said MOS gate dielectric layer;
• forming MOS source/drain regions in said substrate adjacent to said MOS gate, said MOS source/drain regions having oxide layers on a top surface;
• and
• forming MOS sidewall spacers on lateral surfaces of said MOS gate;
• performing a hydrofluoric acid (HF) etch process, by a process which includes exposing an existing top surface of said integrated circuit to an aqueous HF solution, so that a portion or all of said oxide layers on said MOS source/drain regions are removed;
• performing a first SC1 etch process, by a process which includes exposing said existing top surface of said integrated circuit to a first aqueous solution of ammonium hydroxide and hydrogen peroxide;
• performing a piranha process, by a process which includes exposing said existing top surface of said integrated circuit to a mixture including sulfuric acid and hydrogen peroxide;
• performing a second SC1 etch process, by a process which includes exposing said existing top surface of said integrated circuit to a second aqueous solution of ammonium hydroxide and hydrogen peroxide, so that native oxide layers on said top surface of said MOS source/drain regions are less than 2 nanometers thick;
• forming a metal layer on said existing top surface of said integrated circuit;
• heating said integrated circuit so as to react metal in said metal layer with semiconductor material at said top surface of said MOS source/drain regions to form metal silicide layers at an interface between said metal layer and said MOS source/drain regions;
• and
• removing unreacted metal from over said integrated circuit.