Manufacturing method for semiconductor device carrier and manufacturing method for semiconductor package using the same

A manufacturing method for a semiconductor device carrier, wherein the manufacturing method comprises:

• providing a dielectric layer having a first dielectric surface and a second dielectric surface, wherein the dielectric layer encapsulates a plurality of conductive trace layers, and the conductive trace layers extend from the first dielectric surface to the second dielectric surface and comprise a plurality of traces which are mutually isolated from one another;
• forming a plating conductive layer on the second dielectric surface and the traces exposed on the second dielectric surface, wherein the plating conductive layer electrically interconnects every trace;
• forming a surface finishing on at least a portion of each trace exposed on the first dielectric surface by electrolytic plating;
• and
• removing the plating conductive layer to re-expose the second dielectric surface.

A manufacturing method for a semiconductor package, wherein the manufacturing method comprises:

• providing a conductive carrier having a first surface and a second surface opposite to the first surface;
• forming a conductive trace layer on the second surface of the conductive carrier;
• forming a conductive stud layer on the conductive trace layer;
• forming a first dielectric layer to encapsulate the conductive trace layer and the conductive stud layer;
• exposing the conductive stud layer;
• forming a plating conductive layer to envelop the conductive carrier, the first dielectric layer and the exposed base surface of the conductive stud layer;
• forming a cavity on the conductive carrier to expose the conductive trace layer and the first dielectric layer in the cavity;
• forming a first surface finishing on at least a portion of the exposed conductive trace layer in the cavity;
• removing the plating conductive layer;
• disposing a semiconductor device adjacent to the conductive trace layer;
• and
• forming a second dielectric layer to encapsulate the semiconductor device.