Digital Video Physical layer using a Multi-Level Data Code
AssigneeCrestron Electronics, Inc.
InventorPhilip L. Kirkpatrick
Life of this patent
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Abstract
A system for communicating data comprises a clock channel configured to transmit a clock signal at a predetermined rate and at least one data channel configured to transmit data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate. Each block of multi-level symbols comprises a sequence of at least three multi-level symbols. Each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two. The fixed multiple of the clock rate is an integer greater than one.
Claims18
A system comprising:
- (a) a clock channel (150) configured to transmit a clock signal at a predetermined rate;
- and
- (b) at least one data channel (151) configured to transmit data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate;
- (c) wherein each block of multi-level symbols comprises a sequence of at least three multi-level symbols;
- (d) wherein each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two;
- and
- (e) wherein the fixed multiple of the clock rate being an integer greater than one.
A method comprising the steps of:
- (a) transmitting a clock signal at a predetermined rate by a clock channel;
- and
- (b) transmitting data as a sequence of blocks of multi-level symbols at a fixed multiple of the clock rate;
- (c) wherein each block of multi-level symbols comprises a sequence of at least three multi-level symbols;
- (d) wherein each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two;
- and
- (e) wherein the fixed multiple of the clock rate being an integer greater than one.
A method comprising the steps of:
- (a) deriving a code block for each respective data, control, and BIT signal in accordance with a predetermined code by an encoder;
- (b) accepting the code block from the encoder and generating, as an output, the group of multi-level symbols corresponding thereto by a digital to analog converter;
- (c) transmitting the group of multi-level symbols over at least one data channel;
- (d) accepting, as an input, the group of multilevel symbols and generating the code block corresponding thereto by an analog to digital converter;
- and
- (e) accepting the code block from the analog to digital converter and deriving each respective data, control, and BIT signal from the code block in accordance with the predetermined code by a decoder.
A method for transmitting data and controlling signals, the method comprising:
- (a) encoding an eight symbol, alternatively two symbol, binary input data set and producing therefrom a three symbol undenary output data set, wherein the binary input data set comprises:
- (i) a first binary word having two data bits,
- (ii) a second binary word having eight data bits, and
- (iii) a control bit indicating which one of the first and second binary word determines a resultant code;
- and
- (b) decoding a three symbol undenary input data set and producing therefrom an eight symbol, alternatively two symbol, binary output data set, wherein the binary output set comprises:
- (i) a first binary word having two data bits,
- (ii) a second binary word having eight data bits, and
- (iii) a control bit indicating which one of the first and second binary word was determined from the undenary input data set.
A method for transmitting data and controlling signals, the method comprising:
- (a) providing a clock channel operating at a predetermined rate and transmitting a clock signal on a first one of the wire pairs;
- (b) providing at least one data channel, each operating at a same fixed multiple of the clock rate;
- and
- (c) wherein each of the at least one data channel includes:
- (i) an encoder performing the steps of:
- (A) accepting, as an input set, a TMDS “Data Enable” signal, two TMDS control signals, “[C1:C0]”, and eight TMDS data signals, “[D7:D0]”,
- (B) producing, as an output set, a first sequence of three undenary symbols, and
- (C) computing a running digital sum of the undenary symbols of the produced sequence,
- (ii) a digital to analog converter for accepting the first sequence of three undenary symbols and producing therefrom an output varying level analog voltage in synchronization with the clock channel,
- (iii) conditioning and transmitting the varying level analog voltage onto a corresponding further one of the four twisted wire pairs in a pre-emphasis stage,
- (iv) receiving and conditioning the varying level analog voltage from the corresponding further one of the four twisted wire pairs in an equalization stage,
- (v) accepting the varying level analog voltage and producing therefrom a second sequence of three undenary symbols in synchronization with the clock channel by an analog to digital converter,
- (vi) a decoder performing the steps of:
- (A) accepting, as an input set, the second sequence of three undenary symbols, and
- (B) producing, as an output set, a TMDS “Data Enable” signal, two TMDS control signals, “[C1:C0]”, and eight TMDS data signals, “[D7:D0]”.
Dependencies are inferred from the claim text.