Adaptation circuitry and methods for decision feedback equalizers
AssigneeAltera Corporation
InventorsDoris Po Ching Chan, Thungoc M. Tran
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Abstract
Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.
Claims22
Decision feedback equalizer (“DFE”) circuitry for operating on a serial data signal comprising:
- circuitry for delaying a digitized, serial data output signal of the DFE circuitry by passing that signal successively through a plurality of delay circuit elements so that, at any given time, each delay circuit element outputs one respective previous bit from the serial data output signal of the DFE circuitry;
- circuitry for applying a respective scaling factor to an output signal of each of the delay circuit elements to produce a respective feedback signal;
- circuitry for combining the serial data signal with the feedback signals to produce a source signal for the output signal of the DFE circuitry;
- and
- circuitry for determining the scaling factor for each of the feedback signals based on (1) an algebraic sign of error in the output signal of the DFE circuitry and (2) the output signal of the respective delay circuit element.
A method of operating decision feedback equalizer (“DFE”) circuitry comprising:
- producing a plurality of differently delayed versions of an output signal of the DFE circuitry;
- determining an algebraic sign of an error value of the output signal of the DFE circuitry;
- operating on each of the delayed versions with a signal indicative of the algebraic sign to produce a respective further signal associated with each of the delayed versions;
- and
- using the further signal associated with each of the delayed versions to determine a coefficient for weighting each respective delayed version in a combination with a serial data input signal, from which combination the output signal of the DFE circuitry is produced.
Decision feedback equalizer (“DFE”) circuitry for operating on a serial data signal comprising:
- combiner circuitry for combining the serial data signal with a plurality of feedback signals to produce an intermediate signal;
- first, second, and third circuitries for respectively comparing the intermediate signal to (1) a first relatively high reference voltage, (2) a second relatively low reference voltage, and (3) a threshold voltage that is intermediate the first and second reference voltages, an output signal of the third circuitry being a binary output signal of the DFE circuitry and also being used to control selection of which one of binary output signals of the first and second circuitries is used as an error signal;
- circuitry for delaying the output signal of the DFE circuitry by progressively greater amounts of time to produce a plurality of delayed signals, each of which is delayed by a respective one of the amounts;
- circuitry for multiplying each of the delayed signals by the error signal to produce a plurality of product signals, each of which is associated with a respective one of the delayed signals;
- circuitry for using the product signal associated with each of the delayed signals to determine a weighting coefficient for the associated delayed signal;
- and
- circuitry for weighting each of the delayed signals by the weighting coefficient associated with that delayed signal to produce a respective one of the feedback signals.
Dependencies are inferred from the claim text.