Multiplexer circuit

A circuit comprising:

• a first pair of differential input transistors, each coupled between at least an associated first positive clock transistor and ground;
• the first positive clock transistors coupled between differential output nodes and the differential input transistors associated with the first positive clock transistors, the first positive clock transistors being configured to respond to a positive input from a clock;
• a first inductor coupled between the differential output nodes and a voltage source;
• a second pair of differential input transistors, each coupled between at least an associated first negative clock transistor and ground;
• the first negative clock transistors coupled between the differential output nodes and the differential input transistors associated with the first negative clock transistors, the first negative clock transistors being configured to respond to a negative input from the clock;
• and
• the differential output nodes coupled between the first inductor, the first positive clock transistors, and the first negative clock transistors.

A circuit comprising:

• a first positive input transistor coupled between a first differential pair of clock transistors and ground, the first positive input transistor being configured to respond to a first positive input;
• the first differential pair of clock transistors including a first positive clock transistor configured to respond to a positive clock input and a first negative clock transistor configured to respond to a negative clock input, the first positive clock transistor being coupled to a negative output node and an inductor;
• the inductor coupled between the first positive clock transistor and a voltage source;
• a first negative input transistor coupled between a second differential pair of clock transistors and the ground, the first negative input transistor being configured to respond to a first negative input;
• the second differential pair of clock transistors including a second positive clock transistor configured to respond to the positive clock input and a second negative clock transistor configured to respond to the negative clock input, the second positive clock transistor being coupled to a positive output node and the inductor;
• the differential output nodes including the positive output node and the negative output node;
• a second positive input transistor coupled between a third differential pair of clock transistors and ground, the second positive input transistor being configured to respond to a second positive input;
• the third differential pair of clock transistors including a third positive clock configured to respond to the positive clock input and a third negative clock transistor configured to respond to a negative clock input, the third negative clock transistor being coupled to the inductor;
• a second negative input transistor coupled between a fourth differential pair of clock transistors and ground, the second negative input transistor being configured to respond to a second negative input;
• and
• the fourth differential pair of clock transistors including a fourth positive clock transistor configured to respond to the positive clock input and a fourth negative clock transistor configured to respond to the negative clock input, the fourth negative clock transistor being coupled to the inductor;
• wherein the first negative clock transistor, second negative clock transistor, third positive clock transistor, and fourth positive clock transistor are coupled to each other via resistors or directly through a voltage source.