Memory Device Having Multiple Power Modes

A memory controller for controlling a memory device that includes a memory core, a clock receiver, a command interface, and a data interface, the memory controller comprising:

• an interface to provide a command that specifies a write operation during which the memory device inputs data, the write operation consuming an amount of power, the interface to provide the data, associated with the write operation, to the data interface, after a programmable latency period from when the command is provided;
• and
• an interface to provide a signal that indicates to the memory device, a transition to an operating mode in which less power is consumed than the amount of power consumed during the write operation, wherein the transition is one of a plurality of transitions comprising:
• a transition in which the clock receiver is on, the command interface is turned off, and the data interface is turned off;
• and
• a transition in which the clock receiver is turned off, the command interface is turned off, and the data interface is turned off.

A memory controller for controlling a memory device that includes a clock receiver, a locked loop circuit, a command interface, and a data interface separate from the command interface, the memory controller comprising an interface configured to:

• provide, to the command interface, a command that specifies a write operation during which the memory device inputs data, the write operation consuming an amount of power;
• provide the data, associated with the write operation, to the data interface, after a programmable latency period from when the command is provided;
• and
• provide information that controls transitions between a plurality of power modes, the power modes comprising:
• a mode in which the clock receiver is on, the data interface is off and the locked loop circuit is on;
• and
• a mode in which the clock receiver is off, the data interface is off, the locked loop circuit is off, and the command interface is off.

A memory controller for controlling a memory device comprising a memory core, a locked loop circuit, and a clock receiver circuit to receive an external clock signal, wherein the memory controller comprises one or more interfaces configured to:

• provide to a first interface of the memory device, a command that specifies a write operation;
• after a programmable latency period transpires from when the command is provided to the first interface, provide to a second interface of the memory device that is separate from the first interface, write data associated with the write operation;
• and
• provide power mode information to the memory device, wherein the power mode information specifies a mode selected from the group of modes comprising:
• a first mode in which the clock receiver, the first interface, and the second interface are off;
• a second mode in which the clock receiver is on, the first interface and the second interface are off, and the locked loop circuit is in a first power state;
• and
• a third mode in which the clock receiver is on, second interface is off, and the locked loop circuit is in a second power state.

A memory controller for controlling a memory device comprising a memory core, a locked loop circuit, and a clock receiver circuit to receive an external clock signal, wherein the memory controller comprises:

• an interface to provide:
• a command that specifies a write operation to a command interface of the memory device;
• and
• after a programmable latency period transpires from when the command is provided to the command interface, provide to a data interface of the memory device, write data associated with the write operation;
• and
• an interface to provide power mode information to the memory device, wherein the power mode information specifies a mode selected from the group of modes comprising:
• a first mode in which the clock receiver, the command interface, and the data interface are off;
• a second mode in which the clock receiver is on, the command interface and the data interface are off, and the locked loop circuit is in a first power state;
• and
• a third mode in which the clock receiver is on, the data interface is off, and the locked loop circuit is in a second power state.