Electrical fuse memory arrays
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Hung CHEN, Chin-Huang WANG, Yen-Chieh HUANG, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Abstract
Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
Claims20
A memory array comprising:
- a plurality of eFuse memory cells arranged in a plurality of columns;
- and
- a plurality of bit lines;
- wherein
- a column of the plurality of columns of the eFuse memory cells includes:
- a bit line selector;
- a bit line coupled to the bit line selector;
- and
- a set of the plurality of eFuse memory cells;
- a memory cell of the set of the plurality of eFuse memory cells of the column includes a PMOS transistor and an eFuse;
- a drain of the PMOS transistor coupled to a first end of the eFuse;
- a gate of the PMOS transistor coupled to a word line;
- a source of the PMOS transistor coupled to the bit line of the column.
A memory array, comprising:
- a plurality of eFuse memory cells arranged in rows and columns;
- wherein
- at lease one eFuse memory cell includes:
- a PMOS transistor;
- and
- an eFuse;
- a first end of the eFuse coupled to a drain of the PMOS transistor;
- at least one column includes:
- a bit line select device;
- a first plurality of eFuse memory cells in the at least one column;
- and
- a bit line coupling the bit line select device and a plurality of sources of a plurality of PMOS transistors of the first plurality of eFuse memory cells in the at least one column;
- and
- at least one row includes:
- a second plurality of eFuse memory cells in the at least one row;
- a word line coupling a plurality of gates of a plurality of PMOS transistors of the second plurality of eFuse memory cells in the at least one row;
- and
- a voltage source configured to provide a voltage value at a second end of a plurality of eFuses of the second plurality of eFuse memory cells in the at least one row.
A method of operating an eFuse memory cell in a memory array of a plurality of eFuse memory cells, the eFuse memory cell including a PMOS transistor and an eFuse, a first end of the eFuse coupled to a drain of the PMOS transistor, the method comprising:
- activating the PMOS transistor;
- and
- selectively coupling a first power source or a second power source to a bit line coupled to a source of the PMOS transistor;
- wherein the step of selectively coupling comprises:
- using the first power source to generate a current flowing through the bit line and having a first current value sufficient to program the eFuse, if the eFuse memory cell is in a program mode;
- and
- using the second power source to generate the current having a second current value sufficient to read the eFuse, if the eFuse memory cell is in a read mode;
- the first current value differing from the second current value.
Dependencies are inferred from the claim text.