Semiconductor memory device and method of operating the same

A semiconductor memory device, comprising:

• main page buffers coupled to respective main columns and coupled to a data line in response to a plurality of first select signals, respectively;
• redundancy page buffers coupled to respective redundancy columns and to the data line in response to a plurality of second select signals, respectively, and configured to store data, indicating an execution of a program, in response to a plurality of second control signals, respectively;
• an address controller configured to store fail column addresses and to sequentially output the fail column addresses while a first control signal is activated;
• a control logic configured to input data indicating a program pass through the data line while the first control signal is activated and to output a page buffer select signal for selecting the main page buffer associated with the fail column address outputted from the address controller and the redundancy page buffer associated with a redundancy column address to replace the fail column address;
• and
• a page buffer control circuit configured to enable one of the plurality of first select signals in order to select the main page buffer, corresponding to the page buffer select signal of the control logic, and enable one of the plurality of second control signals in order to select the redundancy page buffer, while the first control signal is activated.

A method of operating a semiconductor memory device, comprising:

• inputting a first logical value to latches of main page buffers coupled to a main column and a second logical value to latches of redundancy page buffers coupled to a redundancy column, before starting inputting redundancy data;
• sequentially selecting the main page buffers associated with fail column addresses in order to input the redundancy data;
• and
• changing data of the selected main page buffer into the second logical value and data of the redundancy page buffer coupled to a redundancy column line corresponding to the fail column address into the first logical value.