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US 2012/0057415 A1Published application
Nonvolatile memory device
AssigneeHynix Semiconductor Inc.
InventorYong Deok CHO
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal.
Claims24
A nonvolatile memory device, comprising:
- a number of page buffer groups each comprising a number of normal page buffers;
- I/O lines corresponding to the respective normal page buffers;
- and
- a column decoder generating a column address decoding signal for coupling the normal page buffers and the respective I/O lines in response to a normal control clock signal.
1 more element
A nonvolatile memory device, comprising:
- a normal page buffer unit selectively coupled to a number of I/O lines in response to column address decoding signals and configured to receive or output data;
- a redundancy page buffer unit selectively coupled to the I/O lines in response to redundancy column address decoding signals and configured to receive or output data;
- a normal column decoder configured to generate the column address decoding signals in response to a normal control clock signal and normal pre-decoding signals;
- a redundancy column decoder configured to generate the redundancy column address decoding signals in response to a redundancy control clock signal and redundancy pre-decoding signals;
- and
- a redundancy circuit configured to generate the normal control clock signal and the redundancy control clock signal in response to column address signals.
3 more elements
A nonvolatile memory device, comprising:
- a normal page buffer unit configured to comprise a number of page buffer groups, to electrically couple a number of I/O lines and any one of the page buffer groups in response to a number of normal column address decoding signals, and to receive or output data;
- a redundancy page buffer unit configured to comprise a number of redundancy page buffer groups, to electrically couple the I/O lines and any one of the redundancy page buffer groups in response to a number of redundancy column address decoding signals, and to receive or output data;
- a normal column decoder configured to generate the column address decoding signals in response to a normal control clock signal;
- a redundancy column decoder configured to generate the redundancy column address decoding signals in response to a redundancy control clock signal;
- and
- a redundancy circuit configured to generate the normal control clock signal and the redundancy control clock signal in response to column address signals.
3 more elements
Dependencies are inferred from the claim text.