Latch Based Memory Device
AssigneeInfineon Technologies AG
InventorsSiegmar Koeppe, Winfried Kamp, Julie Aunis
Life of this patent
Estimating the term…
Abstract
A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.
Claims31
A latch based memory device, comprising:
- a first set of latches,
- a first set of multiplexers coupled to the first set of latches, wherein the first set of multiplexers comprises a first set of inputs having at least one data input and a second set of inputs having at least one test input, wherein an output of each of the first set of multiplexers is connected to an input of each of the first set of latches;
- and
- a second set of latches, wherein each of the second set of latches is connectable to one of the first set of latches,
- wherein the first and second sets of latches are controllable with independent enable signals, respectively.
A method of testing a latch based memory device, the latch based memory device comprising a plurality of latches, electrical connections and a circuit environment of the latches, the method comprising:
- testing a storage functionality of the latches during a first test phase, and
- testing a functionality of the electrical connections and the circuit environment of the latches during a second test phase.
A method of testing a latch based memory device comprising:
- connecting at least two pairs of latches with each other so as to form a shift register chain;
- inputting a bit sequence into the shift register chain to shift the bit sequence through the shift register chain;
- outputting a bit sequence shifted through the shift register chain;
- and
- comparing the output bit sequence with the input bit sequence to evaluate the functionality of the at least two pair of latches.
A method for testing a latch based memory device comprising:
- providing an input unit having a plurality of input latches and at least one multiplexer;
- and
- configuring the input unit to operate as at least one of a plurality of latches or at least one scan register with a plurality of control signals,
- wherein the plurality of control signals comprising a plurality of enable signals for the plurality of input latches and at least one select control signal for the at least one multiplexer.
A method for testing a latch based memory device comprising:
- configuring a storage unit having a plurality of storage latches to receive data and operate as a first combinational logic unit;
- providing input data to the storage unit from an input scan register;
- and
- checking at least one output of the storage unit with an output scan register.
Dependencies are inferred from the claim text.