Analog read and write paths in a solid state memory device
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Vishal Sarin
Life of this patent
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Abstract
A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
Claims24
A memory device, comprising:
- an array of memory cells;
- and
- an analog data path coupled to the array, wherein the analog data path acts as a data cache and an input path to access a selected memory cell in the array, wherein the analog data cache comprises a read circuit, the read circuit comprising:
- a voltage storage device;
- and
- a switch configured to selectively connect the voltage storage device to a ramp voltage.
A method of operating a memory device, the method comprising:
- storing a voltage level in an analog data path of the memory device, the voltage level being representative of a desired threshold voltage to be programmed into a selected memory cell;
- programming the selected memory cell;
- biasing the selected memory cell with a ramp voltage;
- storing an indication of a level of the ramped voltage that causes the selected memory cell to start to conduct;
- and
- comparing the stored indication to the stored voltage level to determine if the selected memory cell has been programmed to the desired threshold voltage.
Dependencies are inferred from the claim text.