Semiconductor memory device

A semiconductor memory device comprising:

• a cell array comprising memory cell strings arranged in a matrix;
• voltage generation circuits which are arranged below the cell array, and apply a voltage to the cell array;
• and
• a control circuit which controls the voltage generation circuits,
• each of the memory cell strings comprising:
• a semiconductor layer comprising a pair of pillar portions extending in a direction perpendicular to a substrate and juxtaposed in a column direction, and a connecting portion formed to connect lower ends of the pair of pillar portions;
• control gates extending in a row direction to intersect the pillar portion, and stacked in the direction perpendicular to the substrate;
• and
• memory cell transistors formed at intersections of the pillar portion and the control gates, and connected in series in the direction perpendicular to the substrate,
• wherein in a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target.