System and Method for Shared Sensing MRAM
AssigneeQUALCOMM Incorporated
InventorsJung Pill Kim, Tae Hyun Kim
Life of this patent
Estimating the term…
Abstract
Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array.
Claims45
A magnetic random access memory (MRAM) comprising:
- a resistive memory having a plurality of resistive memory cells;
- a reference node;
- and
- a read mode switch circuit, configured to selectively switch between a first read mode coupling a first two or more of the resistive memory cells to the reference node, and a second read mode coupling a second two or more of the resistive memory cells to the reference node.
A method for magnetic random access memory (MRAM) storage, comprising:
- programming a resistive memory cell of a first MRAM bank as a first bank binary 0 reference cell and a resistive memory cell of the first MRAM bank as a first bank binary 1 reference cell;
- programming a resistive memory cell of a second MRAM bank as a second bank binary 0 reference cell and a resistive memory cell of the second MRAM bank as a second bank binary 1 reference cell;
- generating a reference voltage based on the first bank binary 0 reference cell and the first bank binary 1 reference cell;
- and
- reading a resistance memory cell of the second MRAM bank based on the reference voltage.
A magnetic random access memory (MRAM) storage, comprising:
- means for programming a resistive memory cell of a first MRAM bank as a first bank binary 0 reference cell and a resistive memory cell of the first MRAM memory bank as a first bank binary 1 reference cell;
- means for programming a resistive memory cell of a second MRAM bank as a second bank binary 0 reference cell and a resistive memory cell of the second MRAM memory bank as a second bank binary 1 reference cell;
- means for generating a reference voltage based on the first bank binary 0 reference cell and the first bank binary 1 reference cell;
- and
- means reading a resistance memory cell of the second MRAM bank based on the reference voltage.
A method for magnetic random access memory (MRAM) storage, comprising:
- step of programming a resistive memory cell of a first MRAM bank as a first bank binary 0 reference cell and a resistive memory cell of the first MRAM bank as a first bank binary 1 reference cell;
- step of programming a resistive memory cell of a second MRAM bank as a second bank binary 0 reference cell and a resistive memory cell of the second MRAM bank as a second bank binary 1 reference cell;
- step of generating a reference voltage based on the first bank binary 0 reference cell and the first bank binary 1 reference cell;
- and
- step of reading a resistance memory cell of the second MRAM bank based on the reference voltage.
A computer product having a computer readable medium comprising instructions that, when read and executed by a processor, cause the processor to:
- program a resistive memory cell of a first magnetic random access memory (MRAM) bank as a first bank binary 0 reference cell and a resistive memory cell of the first MRAM bank as a first bank binary 1 reference cell;
- program a resistive memory cell of a second MRAM bank as a second bank binary 0 reference cell and a resistive memory cell of the second MRAM bank as a second bank binary 1 reference cell;
- control a generation of a reference voltage based on the first bank binary 0 reference cell and the first bank binary 1 reference cell;
- and
- control a read of a resistance memory cell of the second MRAM bank based on the reference voltage.
Dependencies are inferred from the claim text.