US 2012/0056769 A1 · METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS

Abstract

Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Claims22

Dependent claims

A timing circuit comprising:

a time to digital conversion (TDC) circuit configured to provide:
a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a first feedback signal, and
a delay signal that is variably delayed relative to the reference clock signal;
a calibration module configured to:
receive the delay signal and a second feedback signal, and
provide a calibration signal to increase and decrease a total delay of the TDC circuit, wherein the total delay of the TDC circuit is based on a time delay of the calibration signal plus a time delay of a correction signal;
and
a correction module configured to receive the timing signal and provide the correction signal, the correction module minimizing harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

5 more elements

A method of controlling timing of signals, the method comprising:

receiving a reference clock signal and first and second feedback signals;
delaying the reference clock signal via N delay cells to provide a delay signal;
generating, at a frequency of the reference clock signal, a timing signal indicative of a timing difference between edges of the reference clock signal and of the first feedback signal;
adjusting the delay cells based on the delay signal, the second feedback signal, and the timing signal to calibrate a total delay of the delay cells and to reduce mismatch among delay cells.

1 more element

Dependencies are inferred from the claim text.

Method and system for time to digital conversion with calibration and correction loops

Life of this patent

Method and system for time to digital conversion with calibration and correction loops

Life of this patent

Abstract

Claims22