Non-linearity correction that is independent of input common mode, temperature variation, and process variation
AssigneeTexas Instrumentals Incorporated
InventorsGanesh Kiran, Visveswaraya Pentakota, Viswanathan Nagarajan
Life of this patent
Estimating the term…
Abstract
In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.
Claims15
An apparatus comprising:
- a sample-and-hold (S/H) circuit that receives an input signal;
- and
- a correction circuit having:
- a plurality of MOS capacitors that are each coupled to the S/H circuit and that each receives the input signal;
- a compensator that receives a common mode voltage;
- and
- a voltage divider that is coupled to the compensator so as to generate a plurality of control voltages relative to the common mode voltage, process variations of the MOS capacitors, and temperature variations of the NMOS capacitors and that is coupled to each of MOS capacitors so as to provide each MOS capacitor with at least one of a plurality of control voltages.
An apparatus comprising:
- a plurality of analog-to-digital converter (ADC) stages coupled in series with one another in a sequence, wherein the first ADC stage of the sequence includes:
- a sample-and-hold (S/H) circuit that receives the analog input signal;
- and
- a correction circuit having:
- a plurality of MOS capacitors that are each coupled to the S/H circuit and that each receive the analog input signal;
- a compensator that receives a common mode voltage;
- and
- a voltage divider that is coupled to the compensator so as to generate a plurality of control voltages relative to the common mode voltage, process variations of the MOS capacitors, and temperature variations of the NMOS capacitors and that is coupled to each of MOS capacitors so as to provide each MOS capacitor with at least one of a plurality of control voltages;
- and
- a digital output circuit that is coupled to each ADC stage and that outputs a digital output signal.
Dependencies are inferred from the claim text.