DLL circuit with dynamic phase-chasing function and method thereof
AssigneeEtron Technology, Inc.
InventorsYu-Sheng Lai, Feng-Chia Chang, Chun Shiah
Life of this patent
Estimating the term…
Abstract
A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.
Claims10
A delay locked loop (DLL) circuit with dynamic phase-chasing function, comprising:
- a voltage control delay line (VCDL) circuit for receiving an input clock signal and a control voltage, and delaying the input clock signal according to the control voltage to generate an output clock signal;
- a predetermined delay circuit for delaying the output clock signal for a predetermined period to generate a feedback clock signal;
- a divisor-adjustable frequency-dividing circuit for dividing frequencies of the input clock signal and the feedback clock signal, respectively, to generate a divided input clock signal and a divided feedback clock signal;
- a phase/frequency detector for comparing phases of the divided input clock signal and the divided feedback clock signal to generate an up signal or a down signal;
- and
- a charge bump for adjusting the control voltage according to the up signal and the down signal;
- wherein the divisor-adjustable frequency-dividing circuit detects an overall loop delay of the input clock signal in the DLL circuit to generate an optimal divisor, and divides the frequencies of the input clock signal and the feedback clock signal according to the optimal divisor.
A method of dynamically adjusting phase-chasing speed for increasing efficiency of a delay loop locked (DLL) circuit, comprising:
- detecting an overall loop delay for an input clock signal in the DLL circuit;
- obtaining an optimal divisor according to the overall loop delay;
- and
- in a phase-locking period of the DLL circuit, dividing frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.
Dependencies are inferred from the claim text.