Semiconductor device and driving method thereof

A driving method for a semiconductor device, the semiconductor device comprises a memory cell including:

• a first transistor comprising a first gate electrode;
• a second transistor comprising;
• a second gate electrode that overlaps with at least a part of one of a source and a drain of the first transistor with a first insulating layer interposed therebetween;
• and
• a second channel formation region over the second gate electrode;
• and
• a wiring over the second transistor with a second insulating layer interposed therebetween,
• wherein one of a source and a drain of the second transistor is electrically connected to the first gate electrode so that a node is formed,
• the driving method comprising the steps of:
• turning on the second transistor so that charge is supplied to the node,
• turning off the second transistor so that charge is held in the node, and
• supplying a second potential to the second gate electrode at least when a first potential is supplied to the wiring in a period during which charge needs to be held in the node,
• wherein the second potential has opposite polarity with the first potential.

A driving method for a semiconductor device, the semiconductor device comprising:

• a plurality of bit lines;
• a plurality of source lines;
• a plurality of write word lines;
• a plurality of write-read word lines;
• and
• a memory cell array comprising a plurality of memory cells, one of the plurality of the memory cells comprising:
• a first transistor including a first gate electrode, a first source region, a first drain region, and a first channel formation region;
• a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region provided so as to overlap at least part of one of the first source region and the first drain region;
• and
• a capacitor,
• wherein one of the plurality of source lines is electrically connected to the first source region,
• wherein one of the plurality of bit lines is electrically connected to the first drain region and the second source electrode,
• wherein one of the plurality of write-read word lines is electrically connected to one electrode of the capacitor,
• wherein one of the write word lines is electrically connected to the second gate electrode,
• wherein the first gate electrode, the second drain electrode, and the other electrode of the capacitor are electrically connected to one another to form a node where charge is held,
• the driving method comprising the steps of:
• supplying a first potential to one of the plurality of write word line and a second potential to the other of the plurality of write word lines in unselected rows at least when a third potential is supplied to the plurality of bit lines in a writing period of the one of the memory cells, and
• supplying a fourth potential to the plurality of write word lines at least when a fifth potential is supplied to the plurality of bit lines in a reading period of the one of the memory cells,
• wherein the first potential, the third potential and the fifth potential have a same polarity, and
• wherein the second potential and the fourth potential have a same polarity that is opposite polarity with the first potential.