Multiphase clock generation circuit
AssigneeFujitsu Limited
InventorMasafumi KONDOU
Life of this patent
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Abstract
A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.
Claims17
A multiphase clock generation circuit comprising:
- a first frequency divider to generate a first intermediate clock and a second intermediate clock in synchronization with a reference clock;
- a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock in synchronization with the first intermediate clock;
- a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock in synchronization with the second intermediate clock;
- a selector, provided between the first frequency divider and the third frequency divider, to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal;
- an error detection circuit to detect an error in a phase relationship between an output clock of the first group and an output clock of the second group when the switching signal indicates a first mode;
- and
- a re-reset circuit to output the switching signal to the selector based on the error in asynchronous with the reference clock.
A multiphase clock generation circuit comprising:
- a first frequency divider to generate a first intermediate clock, a second intermediate clock, a third intermediate clock, and a fourth intermediate clock in synchronization with a reference clock;
- a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock in synchronization with the first intermediate clock;
- a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock in synchronization with the second intermediate clock;
- a selector, provided between the first frequency divider and the third frequency divider, to supply one of the second intermediate clock, the fourth intermediate clock, and a value to the third frequency divider in response to a switching signal;
- and
- a switching signal supply circuit to output the switching signal to the selector and a reset terminal of the third frequency divider based on the output clock of the first group.
Dependencies are inferred from the claim text.