Semiconductor device and method of adjusting characteristic thereof
AssigneeElpida Memory, Inc.
InventorsKoji Kuroki, Daiki Nakashima, Ryuuji Takishita
Life of this patent
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Abstract
To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.
Claims17
A semiconductor device comprising:
- a data output terminal;
- a first buffer that includes a transistor of a first conductivity type, the transistor being arranged between the data output terminal and a first power supply and being controlled in impedance by a first adjustment code including a plurality of pieces of bit information;
- a second buffer that includes a transistor of a second conductivity type, the transistor being arranged between the data output terminal and a second power supply and being controlled in impedance by a second adjustment code including a plurality of pieces of bit information;
- and
- an output control circuit that generates the first and second adjustment codes based on a binary search method, and outputs the first and second adjustment codes to the first and second buffers, respectively.
A semiconductor device comprising:
- a calibration terminal;
- a first counter that outputs a first adjustment code;
- a first replica buffer that is connected between the calibration terminal and a first power supply, and is controlled in impedance by the first adjustment code;
- a first comparator that compares a voltage of the calibration terminal with a first reference voltage;
- and
- a counter control circuit that determines a logic level of the first comparator in synchronization with an update clock, and updates the first adjustment code retained in the first counter from higher-order bits based on the result of determination.
A semiconductor device comprising:
- an output buffer;
- a calibration terminal to be coupled to an external resistor;
- and
- a control circuit coupled to the output buffer and the calibration terminal, controlling an output impedance of the output buffer in response to the external resistor, the control circuit comprising a counter, the output impedance of the output buffer being dependent on a count value of the counter, the count value being represented by a plurality of bits including a most significant bit and a least significant bit, and configured to be changed from one of more significant bits inclusive of the most significant bit.
Dependencies are inferred from the claim text.