Layered chip package and method of manufacturing same

A composite layered chip package comprising a plurality of subpackages stacked, every vertically adjacent two of the subpackages being electrically connected to each other, wherein:

• each of the plurality of subpackages includes:
• a main body having a top surface, a bottom surface and four side surfaces;
• and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body;
• the main body includes:
• a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface;
• a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires;
• and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires;
• each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface;
• the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface;
• the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other;
• the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion;
• the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion;
• and
• for any vertically adjacent two of the subpackages, the plurality of second terminals of the upper one of the subpackages are electrically connected to the plurality of first terminals of the lower one.